Compiling ONNX to Custom RISC-V FPGA accelerator with xDSL

This talk walks through the process of building a compiler pipeline for running a quantized ONNX model on a small RISC-V FPGA accelerator. Using xDSL, I lower the model graph through various levels standard MLIR dialects and custom dialects purpose built for the accelerator hardware. Model execution is split between a soft RISC-V CPU and an 8×8 int8 systolic array accelerator.

The talk will focus on two things; a) that prototyping MLIR like compilers is much more approachable with xDSL and b) exploring the lowering pipeline around converting a quantized GEMM into tiled loops, and then into RISC-V CUSTOM0 instructions to drive the accelerator and how the remaining operations run as normal on the soft CPU.

Corresponding hardware talk in references.

What is the xDSL framework and how can it help with easier prototyping of MLIR like compiler pipelines, without writing C++ or TableGen. Also where does it break down.

How an ONNX model can be lowered step by step through TOSA, linalg, and affine / loop-level IR

What went into building the accelerator ISA and how was the codegen done from the loop IRs.

How to represent quantized tensors and their operations on the int8 device.