Talk Intermediate Presentation is CC BY-SA 4.0, Code is MIT

Building a tiny FPGA accelerator with FOSS tooling

Withdrawn

Session Description

In this talk I will go over the current FOSS ecosystem around FPGA development and what I used to build an 8×8 int8 systolic array for GEMM acceleration.

This project used Amaranth for HDL, LiteX for pre-baked SoC IPs and oss-cad-suite project which provides the tools for synthesis, place and route and bitstream flashing.

The goal of this talk is to show that at least on a hobbyist’s scale, FPGA development is no longer constrained to fully proprietary vendor tooling. Also will explore the limitations of these tools and where they break, so that expectation is more grounded.

Key Takeaways

What the current FOSS FPGA tooling stack looks like.

How Amaranth, LiteX, Yosys, nextPNR and openFPGAloader fit together.

What parts of building were very pleasent today.

What are the rough edges today, around board support, vendor specific features etc.