Open-Source FPGA Image Processing Core

Problem Statement

Most beginners in VLSI and FPGA design lack access to simple, open-source hardware projects that demonstrate real-time image processing using synthesizable RTL. Existing solutions are either too complex, proprietary, or software-only, limiting hands-on learning and reuse.

Proposed Solution

This project proposes an open-source FPGA-based image processing core developed using Verilog HDL. The design implements basic yet practical image processing operations such as grayscale conversion, color inversion, and brightness adjustment. The architecture is modular, lightweight, and suitable for low-cost FPGA boards or simulation-only environments.

System Overview

The system consists of:

A pixel data source (ROM or testbench-driven input)

Image processing modules implemented in RTL

A simple output interface (simulation output or VGA-compatible timing) The design is verified using testbenches and waveform analysis. FPGA deployment is optional but supported.

Key Features

Fully open-source Verilog HDL design

Modular image processing blocks

Simulation-ready (no proprietary tools required)

FPGA-compatible and reusable IP core

Clear documentation for learning and extension

Tech Stack

Verilog HDL

Open-source simulation tools (Icarus Verilog / GTKWave)

Optional FPGA tools (Vivado / Quartus)

Expected Outcome The project will deliver a functional, well-documented open-source hardware core that demonstrates practical image processing on FPGA, making it useful for students, educators, and hardware enthusiasts.