Femtolane

Digital semiconductors (CPUs, GPUs, etc.) are usually designed using a hardware description language like Verilog (a C like language). This description of a circuit needs to go through a flow to be turned into a binary file of shapes (polygons), this flow is called the RTL -> GDSII flow. This project aims to implement such an RTL -> GDSII flow that is natively CPU and GPU parallel to reduce turnaround times of code -> binary conversion from days to hours/minutes for faster iteration.