VerilogViz

VerilogViz is a tool to visualize digital circuits written in Verilog HDL. It can be useful for people learning verilog to visually see what circuits their code generates.

Currently, I have created a simple GUI for editing verilog code on the left and rendering it on the right. But the rendering currently only works for simple circuits and is also restricted to a subset of Verilog (only gate level modelling is supported). The goal was to automatically render the circuit in a manner that is easy to understand for a human. To achieve that, the tool uses some simple heuristics to position the logic gates and then connect them with wires in such a way that the wires don't cross other logic gates.