Compile your own Silicon

What if you could compile a chip?

Software developers are used to writing source code, running a compiler, and producing something that executes on a machine. Hardware has a surprisingly similar idea: write RTL, transform it through synthesis and physical design, generate GDSII, and ultimately fabricate silicon.

This talk explores how far that process can be built using open-source tools.

We will look at tools including Verilator, Yosys, OpenROAD, KLayout and Magic, and examine how they fit together into a modern open-source ASIC workflow. OpenROAD, for example, provides an open RTL-to-GDSII physical-design flow covering stages such as floorplanning, placement, clock-tree synthesis, routing and chip finishing.

We will then introduce the other half of the ecosystem: open PDKs and fabrication. Using SKY130 as a case study, we will distinguish open-source EDA tooling from semiconductor manufacturing itself. The SkyWater/Google SKY130 PDK provides process-design resources for designs targeting SkyWater's 130 nm technology.

Finally, we will look at projects such as Tiny Tapeout that connect the open-source design workflow to actual chip fabrication.

The goal is not to teach the audience how to design a CPU. Instead, the talk asks a broader question:

What happens when the tools for turning hardware source code into physical silicon become open, inspectable and programmable?

• Understand the journey from Verilog RTL to physical GDSII.

• See how Verilator, Yosys and OpenROAD fit into an open ASIC workflow.

• Understand the difference between open-source EDA tools, PDKs and semiconductor fabrication.

• Explore SKY130 and Tiny Tapeout as concrete examples of the open-hardware ecosystem.

• Learn what FOSS changes for hardware education, reproducibility, automation and collaboration.