Breaking Into Chip Design: Building a Digital Design Workflow with Open-Source Tools

Modern chip design is often perceived as inaccessible due to expensive EDA tools and proprietary workflows. However, a growing ecosystem of open-source hardware tools allows students, hobbyists, and developers to learn digital design using only a laptop.

This talk presents a practical digital design workflow covering RTL development in Verilog, simulation and verification using open-source tooling, waveform debugging, and FPGA prototyping. The session includes a walkthrough of designing, simulating, verifying, and prototyping a simple Verilog-based hardware module, highlighting debugging techniques and verification workflows commonly used in digital design. Through real examples, attendees will see how hardware designs can be developed, tested, and validated without relying on costly commercial software.

The session also compares open-source and industry-standard workflows, discusses their strengths and limitations, and provides a roadmap for students interested in VLSI, FPGA development, and computer architecture. Attendees will leave with a clear understanding of how to begin their chip design journey using freely available tools.

1. How to stand up a fully functional, zero-cost digital design environment locally on Linux, macOS, or Windows via WSL.

2. The specific execution steps to compile and simulate Verilog code using Icarus Verilog and Verilator.

3. Visual debugging techniques using trace signals in GTKWave to isolate design flaws and read waveforms.

4. A realistic perspective on how open-source EDA tools translate to industry-standard VLSI/FPGA engineering skills, alongside a learning roadmap for beginners.